The syn1588®Clock_L IP core offers the full syn1588® technology with a large number (paramterizeable during the design) of trigger and IO events supported. The syn1588®Clock_L IP core offers additional ressources for determining the accuracy boundaries of a node. A standard AHB interface (slave) is available for communication to the host processor executing the PTP stack.
Description
Oregano Systems offers a full range of clock cores, which are compatible to the IEEE1588 Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems. The cores differ in footprint, number of I/Os, interface, and supported features.
Features
- fully synchronous to the system clock
- all registers of the core operate with the rising clock edge
- well commented, well structured VHDL cource code
- larger footprint and medium I/O count
- advanced high-performace bus (AHB) slave interface for clock control
- one or more media independent interfaces (MII) for sync message detection
- two event inputs, two trigger outputs, two period outputs, one 1 pulse per second (PPS) output
- generation of interrupt upon several events
- pipelined adder based clock for best synchronization results
- seperate receive and transmit timestamp FIFOs for every MII interface
- clock time format compatible to the IEEE1588 standard
- suited for FPGA as well as ASIC implementations
- enhanced interrupt features for hard real time systems
- upper and lower clock bounds for dependable distributed systems
Brief Data Sheet
- syn1588Clock_L IP core brief data sheet (PDF-File, 82KB)
Ressources & Performance
The following table gives a rough overview of the area consumption of the syn1588®Clock_L IP cores as well as the achieved maximum frequency for selected target technologies.
Note that the actual implementation figures depends on the selected target technology or FPGA device (family, package, speed grade) as well as the constraints (minimum area or maximum frequency) used for implementing the core.
| syn1588®Clock_L IP Core | ||
|---|---|---|
| Technology | Area | Frequency |
| Lattice XP lfxp20cfpbga484-3 |
9890 LUTs 2 BRAMs |
40 MHz |
| Altera CycloneII ep2c5f256c8 |
7124 LEs 6 M4K BRAMs |
40 MHz |
| Altera StratixII ep2s15f484c5 |
6373 ALUTs 4 M4K BRAMs |
55 MHz |
| Xilinx Spartan3E xc3s500e-4ft256 |
5663 LUTs 2 BRAMs |
48 MHz |
| Xilinx Virtex4 xc4vlx15-10sf363 |
5146 LUTs 2 RAMB16 BRAMs |
63 MHz |
Licences
Like for all Oregano Systems' IP cores there are two ways to license the syn1588®Clock_L IP core.
- technology netlist license for a selected FPGA technology or device
- source code license
When ordering the technology netlist license a gate level netlist for the selected target technology is delivered. The IP core is pre-configured during the netlist generation process and cannot be changed by the user.
When ordering the source code license, the complete VHDL source code of the syn1588®Clock_L core is delivered. Thus the customer may change the IP core as required for the application. The VHDL code is fully synthesizeable and requires no special constraints.
There is a complete verification setup for both licensing schemes available that enables system simulation and standard compliance tests.
For additional information on our syn1588® products or a detailed quotation please contact us.