Encrypting data for transport acros networks, the Internet, or via any other media as becomming more and more important. The AES algorithm offers a powerful replacement for the old and well known DES algorithm.
AES (Advanced Encryption Standard) (Advanced Encryption Standard) is a symmetrical encryption. The Rijndael algorithm was developed by Dr. Joan Daemen and Dr. Vincent Rijmen. The algorithm was selected by the NIST (National Institute of Standards and Technology) as winner of the "AES contest".
The AES IP core is available in three versions. They differ in their throughput (measured in clock cycles per en-/decryption) and their resourcen requirements (measured in gates or LUTs).
- High Efficiency Version
- Standard Version
- High Performance Version
The AES IP core is suited for integration in ASIC as well as FPGA designs. The core supports key lengths of 128, 192 and 256 bit. Additional hardware support for CBC operation as well as key storage is available.
Like all our IP cores we offer the AES IP core in two license options
- technology netlist license for a selected FPGA technology/device
- source code license
No matter how perfect an IP core has been desinged there are for every project and customer some special requirements. Adding another interface option for a specific processor or bus system. We will adapt the AES IP core to your project's specific beeds!
You will find detailled technical information of the AES IP Core here. For further question please do not hesitate to contact us.
If you would like to receive a quotation please contact us.